@sstrell
Please refer to my pseudo-code as follows.
I am 100% sure the test C code, verilog code, and everything things are correct.
The axi4lite Verilog code in my project has previously used and verified in my old project, so I confirm Verilog code of Axi4Lite is correct.
My main uncertainty, doubts and concerns are:
1) whether I connect/configured avalon to axi4lite correctly.
2) I left shift 2bits of the bias address of those registers in C code. I don't know whether is correct or not.
Please help to confirm my upper doubts based on the pictures and pseudo-code I pasted.
In Verilog code, I defined registers:
`define SCAN_WADDR_N 6'h18 // 60 <-- 0x18 Left shift 2 bits
`define SCAN_WDATA_N 6'h19 // 64
`define SCAN_WRITE_N 6'h1A // 68
In C code, I access those registers by the following address:
#define FPGA_SCAN_WADDR (FPGA_REGS_ADDR + (0x18<<2))
#define FPGA_SCAN_WDATA (FPGA_REGS_ADDR + (0x19<<2))
#define FPGA_SCAN_WRITE (FPGA_REGS_ADDR + (0x1A<<2))
In system.h in BSP:
#define ALT_MODULE_CLASS_BF5V_0 BF5V
#define BF5V_0_BASE 0x80000 // this address is the same as that in Platform Designer
#define BF5V_0_IRQ -1
#define BF5V_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BF5V_0_NAME "/dev/BF5V_0"
#define BF5V_0_SPAN 256
#define BF5V_0_TYPE "BF5V"
The test C code is:
int main()
{
while(1)
{
FPGA_Write(FPGA_SCAN_WADDR, 0x55AA); // write address
FPGA_Write(FPGA_SCAN_WDATA, 0x33); // write data
FPGA_Write(FPGA_SCAN_WRITE, 0x0001); // write enable signal
FPGA_Write(FPGA_SCAN_WRITE, 0x0000); // clear write enable signal
}
return 1;
}
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