Can't generate 20Mhz clock from Cyclone III Starter Kit

I'm using the Cyclone III Starter Kit along-with some ADC & DAC chips. These chips demand a 20 MHz input clock, which I intend to generate from my Starter board.

After going through the "my_first_fpga_tutorial" - it seemed quite simple to me : Just have an ALTPLL megafunction generate the 20 Mhz output from the 50 Mhz clock input. (osc_clk: Pin_V9)

I tried that, and assigned the generated output clocks to the "HSMC_CLKOUT_n2" & "HSMC_CLKOUT_p2" pins (they are dedicated clock output pins I guess)

I used the same code for the TimeQuest SDC file, as is given in the tutorial (since i've yet to learn what this is):

create_clock -period 20.000 -name osc_clk osc_clk

derive_pll_clocks

derive_clock_uncertainty

Now I test the corresponding output pins on the oscilloscope, but all I see is a very jittery signal (can't trigger it stable on the scope by any means), with a very low frequency (about 100 Hz).

Can anybody help ?