New ContributorManual simulation of a HLS design failed
We are trying to test HLS Compiler by building a simple component for matrix multiplying. The component works and simulates fine by running the co-simulation .exe file produced by the HLS Compiler.
However we are also trying to simulate manually in ModelSim using a verilog testbench (in which the component is instantiated) with NativeLink from Quartus, but the simulation fails with the errors:
# ** Error: (vlog-13069) c:/.../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v(21): near "acl_arb_data": syntax error, unexpected IDENTIFIER.
# ** Error: c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v(21): (vlog-13205) Syntax error found in the scope following 'interface'. Is there a missing '::'?
Intel HLS Compiler version 21.2.0 Build 68.1
Intel Quartus Prime Lite Edition Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
ModelSim Intel FPGA Started Edition 2021.1 Revision 2021.2.
Also tested with ModelSim Intel FPGA Started Edition 2020.1 Revision 2021.2.
Hello,
I'm replying to my own topic for resolving the issue. The problem was the .do file that is generated when executing NativeLink testbench from Quartus marks the source files generated by HLS Compiler as Verilog 2001 instead of SystemVerilog. Perhaps because the files are with the .v extension instead of .sv, even though they contain SystemVerilog specific code?
Replacing all of the -vlog01compat with -sv option in the .do file (and then running the .do file again in ModelSim) allowed the execution of the test bench.E.g.:
vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv} vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v} vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}
Replace with -sv:vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv} vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v} vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}
