Altera Releases Quartus® Prime Pro Edition and FPGA AI Suite version 25.3: Faster Compiles, Smarter

Occasional Contributor

4 months ago

We’re thrilled to announce the immediate availability of Quartus Prime Pro Edition 25.3, along with the simultaneous release of FPGA AI Suite 25.3, a major leap forward in FPGA design productivity. This release delivers smarter tools, deeper insights, and faster compiles, achieving a 6% compile time improvement over 25.1, a 27% reduction since Agilex 7 transitioned to production, as well as improved AI tool ease of use. With enhanced compiler and architecture optimizations, designers can fit more logic using 4% fewer ALMs on average, all while maintaining top-tier Fmax. Whether you're closing timing or accelerating tape-out, Quartus 25.3 helps you go further, faster.

Power & Thermal Analyzer: Smarter, Cooler, More Efficient

Quartus 25.3 expands the Power & Thermal Analyzer into a next-generation tool for smarter, cooler, and more efficient FPGA systems. With unified workflows, advanced thermal modeling, and what-if scenario exploration, designers gain deeper visibility into power consumption and thermal behavior earlier in the cycle. From edge AI to high-performance networking accelerators, this enhanced analyzer helps optimize power budgets, guide heatsink design, and reduce surprises before deployment. This next-generation tool offers:

Unified PTC/PTA workflow with graphical reports, sortable columns, hierarchy first display, resource views, recalculation, partial import/export, error messaging, and standalone installer
What-if scenario exploration to optimize package and ordering part number combinations
Advanced thermal modeling, including heat sink dissipation paths and percentage-based heat flow
Heatsink design guidance for smarter cooling strategies
Enhanced documentation to support power-aware design from concept to deployment

Visual Designer Studio (Beta): A New Era of Design Entry

Say hello to Visual Designer Studio, the successor to Platform Designer, now available in public beta with a no-cost license. Quartus 25.3 introduces early access to Visual Designer Studio, Altera’s fourth generation system design entry tool. Designed for both RTL developers and system integrators, it automates IP connectivity, validates functional correctness, and slashes setup time. With a drag-and-drop interface, Smart Connect automation, and GitHub-hosted examples, Visual Designer Studio empowers teams to architect complex systems with speed and precision. It brings:

Smart Connection automation
System Verilog wrapper generation, hierarchy support, and language templates
Modernized GUI with easy to understand block diagrams
Pattern generation/check IP to accelerate design validation
GitHub-hosted Nios® V example designs for faster prototyping

This intuitive, visual-first environment makes it easier than ever to architect complex systems with speed and precision.

IP Innovations: Smarter Connectivity, Faster Interfaces, Broader Protocol Support

Quartus Prime Pro 25.3 delivers a robust suite of IP updates that push the boundaries of performance, interoperability, and flexibility. From expanded Ethernet and PCIe/CXL support to enhanced video, memory, and functional safety IP, this release equips developers to build next-gen systems across networking, embedded, and safety-critical domains. As you integrate high-speed protocols or tackle FuSa requirements, this new release gives you the tools to do it faster and smarter.

High-Speed Connectivity

Ethernet: Expanded 400G/200G/100G support, TSN MAC examples, and toolkit-enabled TSE Soft IP.
PCIe & CXL: SR-IOV examples, AXI MCDMA CvP support, and CXL 2.0 features like Global Persistent Flush and multi-logical device validation.
JESD & CPRI: JESD204C M > 32 support, full CPRI variant coverage, and updated Serial Lite toolkit.

Multimedia Interfaces

HDMI, SDI, DisplayPort: Enhanced video pipeline support with new diagnostic tools and EDID access.

MIPI CSI-2/DSI-2: Enabled on Agilex 3 for camera/display interfacing.

Memory & Embedded

DDR5/LPDDR5: Speeds up to 5600 MT/s and 5500 MT/s on Agilex 5D.

EMIF Toolkit: Now supports SM HPS EMIF IP.

Soft IP: New I3C controller, enhanced System ID, and FuSa-ready ALT_ECC and FIFO IP.

Soft IP & Functional Safety

Soft I3C Controller: Adds flexibility for sensor and peripheral interfacing.

System ID Enhancements: Timestamp and HASH features with HAL driver support.

ALT_ECC and FIFO IP Updates: Targeting functional safety (FuSa) needs.

Safety Certification Packaging: FSDP support for QPDS workflows.

FPGA AI Suite: DDR-Free Mode Turbo Charges AI Inference

FPGA AI Suite includes new features that significantly advance edge AI inference on Altera FPGAs. Key highlights:

DDR free mode enables instantaneous model switching, lower power, and higher FPS

Example: 27% increase in FPS for RESNET-50 on Agilex 7

Agilex 3 production support, including hostless JTAG design for the Agilex 3 C-Series dev kit.

One-stop installation: available as an option in the Quartus installer.

FPGA AI Suite example designs available in Visual Designer Studio

Additional Highlights in 25.3

Streaming-capable System Console with Python interface

Safety Separation Flow support in Assembler

Unified GUI elements and usability improvements across tools

Containerized installation and new “Embedded-Centric” Quartus Edition

Enhanced embedded development experience through improved Yocto project and KAS build system

FreeRTOS enablement and expanded Nios V drivers support
Windriver VxWorks BSP support for Agilex 5

Next Steps

Quartus Prime and FPGA AI Suite25.3 are built to empower developers with smarter tools, deeper insights, and a more intuitive design experience. By combining performance improvements with intelligent design entry and analysis tools, this release helps teams reduce iterations, close timing faster, and get to market with confidence.

Release 25.3 isn’t just faster—it’s smarter.